ITA Software's Technical Seminar Series

Talk Topic: Multicore-Aware File Cache
Silas Boyd-Wickizer, MIT CSAIL
June 17, 2009

Abstract

In this talk I will present a file cache system that is designed for high performance on multicore chips. Multicore chips will have large amounts of fast on-chip cache memory, along with relatively slow DRAM interfaces. The on-chip cache memory, however, will be fragmented and spread over the chip, making it hard to exploit fully in order to avoid slow DRAM. First, data accessed from many cores may be duplicated in many caches, reducing the amount of distinct data cached. Second, data in a cached distant from the accessing core may be slow to fetch via the cache coherence protocol. Third, software on one core cannot allocate space in the caches tied to other cores (e.g., L1 and L2 caches).

The MCFC (multicore-aware file cache) addresses these challenges for applications that make heavy use of operating systems' file buffer cache. MCFC chooses the on-chip cache in which to cache each file. As an application thread reads file data, MCFC moves it to the core with the on-chip chache that contains the data. This allows the thread to read the data quickly if it is already on-chip; if it is not, moving the thread causes the data to be loaded into the chosen on-chip cache.

An implementation of MCFC runs in Linux on AMD Opteron quad-core chips. For data-intensive applications such as grep, MCFC provides a speedup of 1.8. Microbenchmarks and analysis suggest that, as on-chip cache memory gets larger and further outstrips DRAM interfaces in aggregate throughput, MCFC will provide benefit to a growing range of applications.