ITA Software's Technical Seminar Series

Talk Topic: IA Memory Ordering
Rick Hudson, new Intel Architecture x86/ia64 memory model
December 17, 2008

Abstract

Intel recently published more precise memory ordering principles for the IA32 and Intel Architecture 64 (aka x86) processors. This talk discusses the key principles embodied in this memory ordering and explains some of the software driven motivation behind them. Along the way we discuss issues such as publication safety and how to use the principles to implement the memory models found in high level programming languages.

The presentation is aimed at developers of concurrent shared memory software and will provide a presentation of the principles as well as guidance on how to reason about them.

Bio

Richard L. Hudson is best known for his work in memory management including the invention of the Train Algorithm, the Sapphire Algorithm, the Mississippi Delta Algorithm, and leveraging the transactional memory to enable concurrent garbage collection. He pioneered the use of stack maps which enabled accurate garbage collection in statistically typed languages. He was a driving force behind getting the Intel's x86/Intel 64 Architecture Memory Model articulated and published. Richard joined Intel in 1998 where he has worked on memory management, concurrency, synchronization, and memory model related issues. He went to Shortridge and holds a B.A. degree from Hampshire College and an M.S. degree from the University of Massachusetts.